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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
FEATURES
* Four LVCMOS/LVTTL outputs, 15 typical output impedance * Selectable crystal oscillator interface or LVCMOS single-ended input * Supports the following input frequencies: 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz * RMS phase jitter @ 212.5MHz(2.55MHz - 20MHz): 0.49ps (typical) * Output supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS840004I is a 4 output LVCMOS/LVTTL Synthesizer optimized to generate Fibre Channel HiPerClockSTM reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 26.5625MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL1:0): 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and 53.125MHz. The ICS840004I uses ICS' 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical random rms phase jitter, easily meeting Fibre Channel jitter requirements. The ICS840004I is packaged in a small 20-pin TSSOP package.
ICS
FREQUENCY SELECT FUNCTION TABLE
Input Frequency (MHz) 26.5625 26.5625 26.5625 26.5625 26.04166 Inputs M Divider F_SEL0 Value 0 24 1 0 1 1 24 24 24 24 N Divider Value 3 4 6 12 4 M/N Ratio Value 8 6 4 2 6 Output Frequency Range (MHz) 212.5 159.375 106.25 53.125 156.25
F_SEL1 0 0 1 1 0
BLOCK DIAGRAM
OE Pullup F_SEL1:0 Pullup:Pullup nPLL_SEL Pulldown nXTAL_SEL Pulldown
PIN ASSIGNMENT
2
F_SEL0 nc nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA nc VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 F_SEL1 GND Q0 Q1 VDDO Q2 Q3 GND XTAL_IN XTAL_OUT
XTAL_IN 26.5625MHz
OSC
XTAL_OUT TEST_CLK Pulldown
0
F_SEL1:0
1 Phase Detector
00 01 10 11
Q0
1
VCO
0
N /3 /4 /6 /12 (default)
Q1
ICS840004I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
Q2
M = /24 (fixed)
Q3
G Package Top View
MR
Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840004AGI www.icst.com/products/hiperclocks.html REV. A JUNE 28, 2005
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
Type Input Pullup Description Frequency select pin. LVCMOS/LVTTL interface levels. No connect. Selects between the crystal or TEST_CLK inputs as the PLL reference source. When HIGH, selects TEST_CLK. When LOW, selects XTAL inpus. LVCMOS/LVTTL interface levels. Single-ended LVCMOS/LVTTL clock input. Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the otuputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH, the PLL is bypassed and the output frequency = reference clock frequency/N output divider. LVCMOS/LVTTL interface levels. Analog supply pin. Core supply pin. Crystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input. Power supply ground. Single-ended clock outputs. LVCMOS/LVTTL interface levels. 15 typical output impedence. Output supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1, 20 2, 9 3 4 5 6 Name F_SEL0, F_SEL1 nc nXTAL_SEL TEST_CLK OE MR
Unused Input Input Input Input Pulldown Pulldown Pullup Pulldown
7 8 10 11, 12 13, 19 14, 15 17, 18 16
nPLL_SEL VDDA VDD XTAL_OUT, XTAL_IN GND Q3, Q2, Q1, Q0 VDDO
Input Power Power Input Power Output Power
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance VDD, VDDA, VDDO = 3.465V Power Dissipation Capacitance Input Pullup Resistor Input Pulldown Resistor Output Impedance VDD, VDDA = 3.465V, VDDO = 2.625V VDD, VDDA, VDDO = 2.625V Test Conditions Minimum Typical 4 TBD TBD TBD 51 51 15 Maximum Units pF pF pF pF k k
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REV. A JUNE 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 73.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDDD = VDDA = 3.3V5%, VDDO = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 2.375 Typical 3.3 3.3 3.3 2.5 90 8 5 Maximum 3.465 3.465 3.465 2.625 Units V V V V mA mA mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 2.375 Typical 2.5 2.5 2.5 80 8 5 Maximum 2.625 2.625 2.625 Units V V V mA mA mA
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 3D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5% OR 2.5V5%, OR
VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C
Symbol Parameter VIH VIL Input High Voltage Input Low Voltage Input High Current OE, F_SEL0, F_SEL1 nPLL_SEL, MR, nXTAL_SEL, TEST_CLK OE, F_SEL0, F_SEL1 nPLL_SEL, MR, nXTAL_SEL, TEST_CLK
Test Conditions VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V VDD = VIN = 3.465V or 2.625V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V VDD = 3.465V or 2.625V, VIN = 0V VDDO = 3.3V 5% VDDO = 2.5V 5% VDDO = 3.3V or 2.5V 5%
Minimum Typical 2 1.7 -0.3 -0.3
Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 5 150
Units V V V V A A A A V V
IIH
IIL
Input Low Current
-150 -5 2. 6 1.8 0. 5
VOH VOL
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
V
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pf parallel resonant cr ystal. Test Conditions Minimum Typical 26.5625 50 7 1 Maximum Units MHz pF mW Fundamental
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REV. A JUNE 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
Test Conditions Minimum Typical 212.5 159.375 Maximum Units MHz MHz MHz MHz MHz ps ps ps ps ps ps ps %
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter
fOUT
Output Frequency
156.25 106.25 53.125
tsk(o)
Output Skew; NOTE 1, 2 212.5MHz (2.55MHz - 20MHz) 159.375MHz (1.875MHz - 20MHz)
TBD 0.49 0.55 TBD 0.79 TBD 400
tjit(O)
RMS Phase Jitter (Random); NOTE 3
156.25MHz (1.875MHz - 20MHz) 106.25MHz (637kHz - 5MHz) 53.125MHz (637kHz - 5MHz)
tR / tF
Output Rise/Fall Time
20% to 80%
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C
Symbol Parameter Test Conditions Minimum Typical 212.5 159.375 fOUT Output Frequency 156.25 106.25 53.125 Maximum Units MHz MHz MHz MHz MHz ps ps ps ps ps ps ps %
tsk(o)
Output Skew; NOTE 1, 2 212.5MHz (2.55MHz - 20MHz) 159.375MHz (1.875MHz - 20MHz)
TBD 0.46 0.54 0.57 0.73 0.63 450
tjit(O)
RMS Phase Jitter (Random); NOTE 3
156.25MHz (1.875MHz - 20MHz) 106.25MHz (637kHz - 5MHz) 53.125MHz (637kHz - 5MHz)
t R / tF
Output Rise/Fall Time
20% to 80%
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot.
840004AGI
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REV. A JUNE 28, 2005
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
Test Conditions Minimum Typical 212.5 159.375 Maximum Units MHz MHz MHz MHz MHz ps ps ps ps ps ps ps %
TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = -40C TO 85C
Symbol Parameter
fOUT
Output Frequency
156.25 106.25 53.125
tsk(o)
Output Skew; NOTE 1, 2 212.5MHz (2.55MHz - 20MHz) 159.375MHz (1.875MHz - 20MHz)
TBD 0.51 0.51 0.54 0.72 0.71 450
tjit(O)
RMS Phase Jitter (Random); NOTE 3
156.25MHz (1.875MHz - 20MHz) 106.25MHz (637kHz - 5MHz) 53.125MHz (637kHz - 5MHz)
tR / tF
Output Rise/Fall Time
20% to 80%
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot.
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REV. A JUNE 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 2.05V5% 1.25V5%
VDD , VDDA, VDDO
SCOPE
Qx
VDD , VDDA
SCOPE
VDDO GND
Qx
LVCMOS
GND
LVCMOS
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
1.25V5%
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
VDD , VDDA, VDDO
SCOPE
Qx
Phase Noise Mask
LVCMOS
GND
f1
Offset Frequency
f2
-1.25V5%
RMS Jitter = Area Under the Masked Phase Noise Plot
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
V
Qx
DDO
RMS PHASE JITTER
80% 20% tR tF 80% 20%
2
V
Qy
DDO
Clock Outputs
2 tsk(o)
OUTPUT SKEW
V
DDO
OUTPUT RISE/FALL TIME
Q0:Q3
t PW
t
2
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840004I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA.
3.3V or 2.5V VDD .01F V DDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840004I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 26.5625MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332
Figure 2. CRYSTAL INPUt INTERFACE
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REV. A JUNE 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
and C2=22pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. 1K pullup or pulldown resistors can be used for the logic control input pins.
LAYOUT GUIDELINE
Figure 3 shows a schematic example of the ICS840004I. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18 pF parallel resonant 26.5625MHz crystal is used. The C1=22pF
Logic Control Input Examples
VDD
Set Logic Input to '1'
RU1 1K
VDD
Set Logic Input to '0'
RU2 Not Install
VDD=3.3V VDDO=3.3V
R3 36 Zo = 50 Ohm
To Logic Input pins
RD1 Not Install RD2 1K
To Logic Input pins
U1 VDDO 1 2 3 4 5 6 7 8 9 10 F_SEL0 nc nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA nc VDD F_SEL1 GND Q0 Q1 VDDO Q2 Q3 GND XTAL_IN XTAL_OUT 20 19 18 17 16 15 14 13 12 11 Zo = 50 Ohm ICS840004I XTAL_OUT C2 22pF X1 XTAL_IN C5 0.1u R4 100 LVCMOS LVCMOS
VDD VDD VDDA R2 10 C3 10uF VDD C4 0.01u C6 0.1u
VDD R5 100
If not using the crystal input, it can be left floating. For additional protection the XTAL_IN pin can be tied to ground.
C1 22pF
Optional Termination
Unused outputs can be left floating. There should be no trace attached to unused outputs. Device characterized and specification limits set with all outputs terminated.
FIGURE 3. ICS840004I SCHEMATIC EXAMPLE
RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS840004I is: 3085
840004AGI www.icst.com/products/hiperclocks.html REV. A JUNE 28, 2005
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
20 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
SYMBOL MIN N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 20 1.20 0.15 1.05 0.30 0.20 6.60 Millimeters MAX
Reference Document: JEDEC Publication 95, MO-153
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REV. A JUNE 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS840004AGI ICS840004AGIT Marking ICS840004AGI ICS840004AGI Package 20 Lead TSSOP 20 Lead TSSOP Shipping Packaging tube 2500 tape & reel Temperature -40C to 85C -40C to 85C
The aforementioned trademarks, HiPerClockSTM and FEMTOCLOCKSTM are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840004AGI www.icst.com/products/hiperclocks.html REV. A JUNE 28, 2005
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